The quality of the distribution of power within a semiconductor device impacts the performance of the semiconductor device in terms of frequency and power. The frequency of the semiconductor device is determined by the worst-case transient droop seen by a circuit when it switches. The active power dissipation is determined by the square of the voltage that the circuit recovers to after the switching has stopped. Taken together, these performance penalties reduce the anticipated gains made by advancing to a next generation semiconductor process by roughly half.
The quality of the distribution of clock signals within the semiconductor device also impacts the performance of the semiconductor device in terms of frequency. Modern semiconductor devices have poor matching between individual devices or wires, yet it is desirable to minimize the skew among the numerous branches of a clock distribution network. Minimizing the delay through the clock distribution network reduces error. Wire propagation delay accounts for roughly half of the total clock distribution delay.